Datapath management in a memory controller

ABSTRACT

A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

BACKGROUND

This application relates to the operation of nonvolatile memorycontrollers such as flash memory controllers, and, more specifically, tosystems and methods of managing elements within such memory controllersin an efficient manner.

Solid-state memory capable of nonvolatile storage of charge,particularly in the form of EEPROM and flash EEPROM packaged as a smallform factor card, has recently become the storage of choice in a varietyof mobile and handheld devices, notably information appliances andconsumer electronics products. Unlike RAM (random access memory) that isalso solid-state memory, flash memory is non-volatile, and retaining itsstored data even after power is turned off. Also, unlike ROM (read onlymemory), flash memory is rewritable similar to a disk storage device. Inspite of the higher cost, flash memory is increasingly being used inmass storage applications. Conventional mass storage, based on rotatingmagnetic medium such as hard drives and floppy disks, is unsuitable forthe mobile and handheld environment. This is because disk drives tend tobe bulky, are prone to mechanical failure and have high latency and highpower requirements. These undesirable attributes make disk-based storageimpractical in most mobile and portable applications. On the other hand,flash memory, both embedded and in the form of a removable card isideally suited in the mobile and handheld environment because of itssmall size, low power consumption, high speed and high reliabilityfeatures.

Flash EEPROM is similar to EEPROM (electrically erasable andprogrammable read-only memory) in that it is a non-volatile memory thatcan be erased and have new data written or “programmed” into theirmemory cells. Both utilize a floating (unconnected) conductive gate, ina field effect transistor structure, positioned over a channel region ina semiconductor substrate, between source and drain regions. A controlgate is then provided over the floating gate. The threshold voltagecharacteristic of the transistor is controlled by the amount of chargethat is retained on the floating gate. That is, for a given level ofcharge on the floating gate, there is a corresponding voltage(threshold) that must be applied to the control gate before thetransistor is turned “on” to permit conduction between its source anddrain regions. In particular, flash memory such as Flash EEPROM allowsentire blocks of memory cells to be erased at the same time.

Nonvolatile memory devices are also manufactured from memory cells witha dielectric layer for storing charge. Instead of the conductivefloating gate elements described earlier, a dielectric layer is used.Such memory devices utilizing dielectric storage element have beendescribed by Eitan et al., “NROM: A Novel Localized Trapping, 2-BitNonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11,November 2000, pp. 543-545. An ONO dielectric layer extends across thechannel between source and drain diffusions. The charge for one data bitis localized in the dielectric layer adjacent to the drain, and thecharge for the other data bit is localized in the dielectric layeradjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and6,011,725 disclose a nonvolatile memory cell having a trappingdielectric sandwiched between two silicon dioxide layers. Multi-statedata storage is implemented by separately reading the binary states ofthe spatially separated charge storage regions within the dielectric.

In addition to flash memory, other forms of nonvolatile memory may beused in nonvolatile memory systems. For example Ferroelectric RAM(FeRAM, or FRAM) uses a ferroelectric layer to record data bits byapplying an electric field that orients the atoms in a particular areawith an orientation that indicates whether a “1” or a “0” is stored.Magnetoresistive RAM (MRAM) uses magnetic storage elements to store databits. Phase-Change memory (PCME, or PRAM) such as Ovonic Unified Memory(OUM) uses phase changes in certain materials to record data bits.Various other nonvolatile memories are also in use or proposed for usein nonvolatile memory systems.

Nonvolatile memory systems, such as flash memory systems are commonlyprovided in the form of a memory card or flash drive that is removablyconnected with a variety of hosts such as a personal computer, a cameraor the like, but may also be embedded within such host systems. Whenwriting data to the memory, the host typically assigns unique logicaladdresses to sectors, clusters or other units of data within acontinuous virtual address space of the memory system. Like a diskoperating system (DOS), the host writes data to, and reads data from,addresses within the logical address space of the memory system. Amemory controller is typically provided within the memory system totranslate logical addresses received from the host into physicaladdresses within the memory array, where the data are actually stored,and then keeps track of these address translations. The memorycontroller may perform a variety of other functions also.

A memory controller chip is typically formed as an ASIC that is designedto perform the particular functions needed in a particular memorysystem. These functions may include address translation as describedabove, Error Correction Coding (ECC) and/or other redundancy schemessuch as Exclusive OR (XOR), management of multiple memory chips on oneor more memory busses, encryption/decryption, and management ofcommunication with a host through a host interface.

FIG. 1 shows an example of a prior art memory system which includes aflash memory, a memory controller, and a host interface, all enclosed ina housing that provides physical protection. While the flash memory isshown a single unit in FIG. 1, it may be made up of multiple memorychips (on one or more memory busses) that are all under the control ofthe memory controller. The memory controller, or ASIC, performs manyfunctions in this memory system. In order to keep memory controllercosts down, it is desirable to efficiently use the resources provided ina memory controller.

SUMMARY

According to a general aspect of the invention, a nonvolatile memorycontroller that includes multiple datapath units, each with separatecontext queues allowing separate operation, coordinates operation ofdifferent datapath units. A datapath control unit may manage operationsof different datapath units to provide improved performance in certainsituations. For example, when a stream of data is detected, the datapathcontrol unit may prioritize the data of the stream so that it passesfrom datapath unit to datapath unit without interruption. Data that isreceived out of order from a memory bus may be reordered by a datapathcontrol unit. When a particular operation is likely to take a long time,contexts associated with the operation may be given lower priority untilthe operation is completed. In some cases, a datapath unit maycommunicate directly with another datapath unit so that a datapathcontrol unit is not needed (i.e. there is direct communication betweendatapath units rather than through a datapath control unit). A broadcastcommunication from one datapath unit may cause other datapath units toprioritize particular data (e.g. data of a data stream).

An example of a method of operating a nonvolatile memory controllerincludes: maintaining a first queue of contexts for a first datapathunit that acts on data between a host interface of the memory controllerand a nonvolatile memory bus; maintaining a second queue of contexts fora second datapath unit that acts on data in series with the firstdatapath unit between the host interface and the nonvolatile memory bus;generating an output that indicates a current operation of the firstdatapath unit; and in response to the output, changing priority ofcontexts of the second queue of contexts for the second datapath unit.

The output may be sent directly from the first datapath unit to thesecond datapath unit. The output may be sent from the first datapathunit to a datapath control unit that is in communication with the firstdatapath unit and the second datapath unit, the datapath control unitmanaging context prioritization for the first datapath unit and thesecond datapath unit. The datapath control unit may manage contextprioritization by maintaining a weighted table of commands, prioritiesof contexts associated with commands changing according to weighting oftheir respective commands. The output may indicate that the firstdatapath unit is acting on data in response to a host read command andweighting associated with the host read command may be modified toprioritize contexts associated with the host read command in the secondqueue of contexts for the second datapath unit. Modification of theweighting associated with the host read command may also prioritizecontexts associated with the host read command in at least a third queueof contexts for a third datapath unit in series with the first andsecond datapath units. The first datapath unit may be a flash interfacemodule that is connected to the nonvolatile memory bus, the seconddatapath unit may be an Error Correction Code (ECC) machine, and thethird datapath unit may be one of: an Exclusive OR (XOR) unit, or a dataencryption/decryption unit. The output may indicate that the firstdatapath unit is acting on data in response to a host write command andweighting associated with the host write command may be modified toprioritize contexts associated with the host write command in the secondqueue of contexts for the second datapath unit. The first datapath unitmay be a host interface unit and the second datapath unit may be one of:an ECC machine, an XOR unit, or a data encryption/decryption unit. Theoutput may indicate that a command should be weighted so that contextsassociated with the command have lower or higher priority. The datapathcontrol unit may apply a weighting scheme to provide data in sequentialorder to the host interface of the memory controller when the data isreceived out of sequential order from the nonvolatile memory bus. Thedatapath control unit may apply a weighting scheme to stream data fromthe host interface to the memory bus, or to stream data from the memorybus to the host interface. The datapath control unit may apply atime-based adjustment of weighting so that commands increase in priorityaccording to the amount of time they remain uncompleted.

An example of a nonvolatile memory controller includes: a hostinterface; a memory bus; a first datapath unit between the hostinterface and the memory bus; a first context queue that containscontexts for the first datapath unit; a second datapath unit connectedin series with the first datapath unit between the host interface andthe memory bus; a second context queue that contains contexts for thesecond datapath unit; and a datapath control unit connected to the firstdatapath unit and the second datapath unit, the datapath control unitprioritizing contexts in the first and second context queues for thefirst and second datapath units.

The datapath control unit may include a tag cache that contains entriescorresponding to commands, each entry having a weighting that indicatespriority of corresponding contexts in the first and second contextqueues. The tag cache may be formed by a Content Addressable Memory(CAM). The first datapath unit may be a nonvolatile memory interfaceunit and the second datapath unit may be an Error Correction Code (ECC)unit. A third datapath unit may be connected in series with the firstand second datapath units between the host interface and the memory bus.The at least a third datapath unit may include at least one of: (a) anExclusive OR (XOR) unit, or (b) an encryption unit. A first set of databuffers may be connected to the first datapath unit and a second set ofdata buffers may be connected to the second set of datapath unit. Thememory bus may be a NAND flash memory bus. The memory bus may be athree-dimensional nonvolatile memory bus.

Various aspects, advantages, features and embodiments of the presentinvention are included in the following description of exemplaryexamples thereof, which description should be taken in conjunction withthe accompanying drawings. All patents, patent applications, articles,other publications, documents and things referenced herein are herebyincorporated herein by this reference in their entirety for allpurposes. To the extent of any inconsistency or conflict in thedefinition or use of terms between any of the incorporated publications,documents or things and the present application, those of the presentapplication shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically the main hardware components of amemory system suitable for implementing the present invention.

FIG. 2 illustrates schematically a non-volatile memory cell.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that the floating gate may be selectively storing at any one time atfixed drain voltage.

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel.

FIGS. 6A-6C illustrate an example of programming a population of 4-statememory cells.

FIG. 7 illustrates a memory system including multiple dies connected toa memory controller by a memory bus.

FIG. 8 illustrates a memory controller having multiple datapath units.

FIG. 9A illustrates operation of a broadcast command by a datapath unitto prioritize a data stream.

FIG. 9B illustrates a tail portion of the data stream of FIG. 9A passingalong the datapath.

FIG. 10 illustrates a datapath control unit in communication withmultiple datapath units.

FIG. 11 illustrates a prioritization table maintained as a tag cache inCAM.

FIGS. 12A-C illustrate reordering of data along a datapath by a datapathcontrol unit.

FIG. 13 illustrates reordering of data between a memory bus and a hostinterface.

DETAILED DESCRIPTION

Memory System

Semiconductor memory devices include volatile memory devices, such asdynamic random access memory (“DRAM”) or static random access memory(“SRAM”) devices, non-volatile memory devices, such as resistive randomaccess memory (“ReRAM”), electrically erasable programmable read onlymemory (“EEPROM”), flash memory (which can also be considered a subsetof EEPROM), ferroelectric random access memory (“FRAM”), andmagnetoresistive random access memory (“MRAM”), and other semiconductorelements capable of storing information. Furthermore, each type ofmemory device may have different configurations. For example, flashmemory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, inany combinations. By way of non-limiting example, passive semiconductormemory elements include ReRAM device elements, which in some embodimentsinclude a resistivity switching storage element, such as an anti-fuse,phase change material, etc., and optionally a steering element, such asa diode, etc. Further by way of non-limiting example, activesemiconductor memory elements include EEPROM and flash memory deviceelements, which in some embodiments include elements containing a chargestorage region, such as a floating gate, conductive nanoparticles or acharge storage dielectric material.

Multiple memory elements may be configured so that they are connected inseries or such that each element is individually accessible. By way ofnon-limiting example, NAND devices contain memory elements (e.g.,devices containing a charge storage region) connected in series. Forexample, a NAND memory array may be configured so that the array iscomposed of multiple strings of memory in which each string is composedof multiple memory elements sharing a single bit line and accessed as agroup. In contrast, memory elements may be configured so that eachelement is individually accessible, e.g., a NOR memory array. One ofskill in the art will recognize that the NAND and NOR memoryconfigurations are exemplary, and memory elements may be otherwiseconfigured.

The semiconductor memory elements of a single device, such as elementslocated within and/or over the same substrate or in a single die, may bedistributed in two or three dimensions, such as a two dimensional arraystructure or a three dimensional array structure.

In a two dimensional memory structure, the semiconductor memory elementsare arranged in a single plane or single memory device level. Typically,in a two dimensional memory structure, memory elements are located in aplane (e.g., in an x-z direction plane) which extends substantiallyparallel to a major surface of a substrate that supports the memoryelements. The substrate may be a wafer over which the layers of thememory elements are deposited and/or in which memory elements are formedor it may be a carrier substrate which is attached to the memoryelements after they are formed.

The memory elements may be arranged in the single memory device level inan ordered array, such as in a plurality of rows and/or columns.However, the memory elements may be arranged in non-regular ornon-orthogonal configurations as understood by one of skill in the art.The memory elements may each have two or more electrodes or contactlines, such as bit lines and word lines.

A three dimensional memory array is organized so that memory elementsoccupy multiple planes or multiple device levels, forming a structure inthree dimensions (i.e., in the x, y and z directions, where the ydirection is substantially perpendicular and the x and z directions aresubstantially parallel to the major surface of the substrate).

As a non-limiting example, each plane in a three dimensional memoryarray structure may be physically located in two dimensions (one memorylevel) with multiple two dimensional memory levels to form a threedimensional memory array structure. As another non-limiting example, athree dimensional memory array may be physically structured as multiplevertical columns (e.g., columns extending substantially perpendicular tothe major surface of the substrate in the y direction) having multipleelements in each column and therefore having elements spanning severalvertically stacked memory planes. The columns may be arranged in a twodimensional configuration, e.g., in an x-z plane, thereby resulting in athree dimensional arrangement of memory elements. One of skill in theart will understand that other configurations of memory elements inthree dimensions will also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memoryarray, the memory elements may be connected together to form a NANDstring within a single horizontal (e.g., x-z) plane. Alternatively, thememory elements may be connected together to extend through multiplehorizontal planes. Other three dimensional configurations can beenvisioned wherein some NAND strings contain memory elements in a singlememory level while other strings contain memory elements which extendthrough multiple memory levels. Three dimensional memory arrays may alsobe designed in a NOR configuration and in a ReRAM configuration.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above and/or within a single substrate, such asa semiconductor wafer. In a monolithic three dimensional array thelayers of each level of the array are formed on the layers of eachunderlying level of the array. One of skill in the art will understandthat layers of adjacent levels of a monolithic three dimensional memoryarray may be shared or have intervening layers between memory levels. Incontrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device. For example,non-monolithic stacked memories have been constructed by forming memorylevels on separate substrates and adhering the memory levels atop eachother. The substrates may be thinned or removed from the memory levelsbefore bonding, but as the memory levels are initially formed overseparate substrates, such memories are not monolithic three dimensionalmemory arrays. Further, multiple two dimensional memory arrays or threedimensional memory arrays (monolithic or non-monolithic) may be formedseparately and then packaged together to form a stacked-chip memorydevice.

One of skill in the art will recognize that this invention is notlimited to the two dimensional and three dimensional exemplarystructures described but cover all relevant memory structures within thespirit and scope of the invention as described herein and as understoodby one of skill in the art.

FIG. 1 illustrates schematically the main hardware components of amemory system suitable for implementing the present invention. Thememory system 90 typically operates with a host 80 through a hostinterface. The memory system is typically in the form of a memory cardor an embedded memory system. The memory system 90 includes a memory 200whose operations are controlled by a controller 100. The memory 200comprises one or more array of non-volatile memory cells distributedover one or more integrated circuit chip. The controller 100 includes aninterface 110, a processor 120, an optional coprocessor 121, ROM 122(read-only-memory), RAM 130 (random access memory) and optionallyprogrammable nonvolatile memory 124. The interface 110 has one componentinterfacing the controller to a host and another component interfacingto the memory 200. Firmware stored in nonvolatile ROM 122 and/or theoptional nonvolatile memory 124 provides codes for the processor 120 toimplement the functions of the controller 100. Error correction codesmay be processed by the processor 120 or the optional coprocessor 121.In an alternative embodiment, the controller 100 is implemented by astate machine (not shown.) In yet another embodiment, the controller 100is implemented within the host.

Physical Memory Structure

FIG. 2 illustrates schematically a non-volatile memory cell. The memorycell 10 can be implemented by a field-effect transistor having a chargestorage unit 20, such as a floating gate or a dielectric layer. Thememory cell 10 also includes a source 14, a drain 16, and a control gate30.

There are many commercially successful non-volatile solid-state memorydevices being used today. These memory devices may employ differenttypes of memory cells, each type having one or more charge storageelement.

Typical non-volatile memory cells include EEPROM and flash EEPROM.Examples of EEPROM cells and methods of manufacturing them are given inU.S. Pat. No. 5,595,924. Examples of flash EEPROM cells, their uses inmemory systems and methods of manufacturing them are given in U.S. Pat.Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421and 6,222,762. In particular, examples of memory devices with NAND cellstructures are described in U.S. Pat. Nos. 5,570,315, 5,903,495,6,046,935. Also, examples of memory devices utilizing dielectric storageelements have been described by Eitan et al., “NROM: A Novel LocalizedTrapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters,vol. 21, no. 11, November 2000, pp. 543-545, and in U.S. Pat. Nos.5,768,192 and 6,011,725.

In practice, the memory state of a cell is usually read by sensing theconduction current across the source and drain electrodes of the cellwhen a reference voltage is applied to the control gate. Thus, for eachgiven charge on the floating gate of a cell, a corresponding conductioncurrent with respect to a fixed reference control gate voltage may bedetected. Similarly, the range of charge programmable onto the floatinggate defines a corresponding threshold voltage window or a correspondingconduction current window.

Alternatively, instead of detecting the conduction current among apartitioned current window, it is possible to set the threshold voltagefor a given memory state under test at the control gate and detect ifthe conduction current is lower or higher than a threshold current(cell-read reference current). In one implementation the detection ofthe conduction current relative to a threshold current is accomplishedby examining the rate the conduction current is discharging through thecapacitance of the bit line.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that the floating gate may be selectively storing at any one time. Withfixed drain voltage bias, the four solid I_(D) versus V_(CG) curvesrepresent four possible charge levels that can be programmed on afloating gate of a memory cell, respectively corresponding to fourpossible memory states. As an example, the threshold voltage window of apopulation of cells may range from 0.5V to 3.5V. Seven possibleprogrammed memory states “0”, “1”, “2”, “3”, “4”, “5”, “6”, respectivelyand one erased state (not shown) may be demarcated by partitioning thethreshold window into regions in intervals of 0.5V each. For example, ifa reference current, IREF of 2 μA is used as shown, then the cellprogrammed with Q1 may be considered to be in a memory state “1” sinceits curve intersects with I_(REF) in the region of the threshold windowdemarcated by VCG=0.5V and 1.0V. Similarly, Q4 is in a memory state “5”.

As can be seen from the description above, the more states a memory cellis made to store, the more finely divided is its threshold window. Forexample, a memory device may have memory cells having a threshold windowthat ranges from −1.5V to 5V. This provides a maximum width of 6.5V. Ifthe memory cell is to store 16 states, each state may occupy from 200 mVto 300 mV in the threshold window. This will require higher precision inprogramming and reading operations in order to be able to achieve therequired resolution.

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string. A NAND string 50 comprises of a series of memorytransistors M1, M2, . . . Mn (e.g., n=4, 8, 16 or higher) daisy-chainedby their sources and drains. A pair of select transistors S1, S2controls the memory transistor chain's connection to the external worldvia the NAND string's source terminal 54 and drain terminal 56respectively. In a memory array, when the source select transistor S1 isturned on, the source terminal is coupled to a source line (see FIG.4B). Similarly, when the drain select transistor S2 is turned on, thedrain terminal of the NAND string is coupled to a bit line of the memoryarray. Each memory transistor 10 in the chain acts as a memory cell. Ithas a charge storage element 20 to store a given amount of charge so asto represent an intended memory state. A control gate 30 of each memorytransistor allows control over read and write operations. As will beseen in FIG. 4B, the control gates 30 of corresponding memorytransistors of a row of NAND string are all connected to the same wordline. Similarly, a control gate 32 of each of the select transistors S1,S2 provides control access to the NAND string via its source terminal 54and drain terminal 56 respectively. Likewise, the control gates 32 ofcorresponding select transistors of a row of NAND string are allconnected to the same select line.

When an addressed memory transistor 10 within a NAND string is read oris verified during programming, its control gate 30 is supplied with anappropriate voltage. At the same time, the rest of the non-addressedmemory transistors in the NAND string 50 are fully turned on byapplication of sufficient voltage on their control gates. In this way, aconductive path is effectively created from the source of the individualmemory transistor to the source terminal 54 of the NAND string andlikewise for the drain of the individual memory transistor to the drainterminal 56 of the cell. Memory devices with such NAND string structuresare described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A. Alongeach column of NAND strings, a bit line such as bit line 36 is coupledto the drain terminal 56 of each NAND string. Along each bank of NANDstrings, a source line such as source line 34 is coupled to the sourceterminals 54 of each NAND string. Also the control gates along a row ofmemory cells in a bank of NAND strings are connected to a word line suchas word line 42. The control gates along a row of select transistors ina bank of NAND strings are connected to a select line such as selectline 44. An entire row of memory cells in a bank of NAND strings can beaddressed by appropriate voltages on the word lines and select lines ofthe bank of NAND strings.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel. FIG. 5essentially shows a bank of NAND strings 50 in the memory array 210 ofFIG. 4B, where the detail of each NAND string is shown explicitly as inFIG. 4A. A physical page, such as the page 60, is a group of memorycells enabled to be sensed or programmed in parallel. This isaccomplished by a corresponding page of sense amplifiers 212. The sensedresults are latched in a corresponding set of latches 214. Each senseamplifier can be coupled to a NAND string via a bit line. The page isenabled by the control gates of the cells of the page connected incommon to a word line 42 and each cell accessible by a sense amplifieraccessible via a bit line 36. As an example, when respectively sensingor programming the page of cells 60, a sensing voltage or a programmingvoltage is respectively applied to the common word line WL3 togetherwith appropriate voltages on the bit lines.

Physical Organization of the Memory

One important difference between flash memory and other of types ofmemory is that a cell must be programmed from the erased state. That isthe floating gate must first be emptied of charge. Programming then addsa desired amount of charge back to the floating gate. It does notsupport removing a portion of the charge from the floating gate to gofrom a more programmed state to a lesser one. This means that updatedata cannot overwrite existing one and must be written to a previousunwritten location.

Furthermore erasing is to empty all the charges from the floating gateand generally takes appreciable time. For that reason, it will becumbersome and very slow to erase cell by cell or even page by page. Inpractice, the array of memory cells is divided into a large number ofblocks of memory cells. As is common for flash EEPROM systems, the blockis the unit of erase. That is, each block contains the minimum number ofmemory cells that are erased together. While aggregating a large numberof cells in a block to be erased in parallel will improve eraseperformance, a large size block also entails dealing with a largernumber of update and obsolete data.

Each block is typically divided into a number of physical pages. Alogical page is a unit of programming or reading that contains a numberof bits equal to the number of cells in a physical page. In a memorythat stores one bit per cell, one physical page stores one logical pageof data. In memories that store two bits per cell, a physical pagestores two logical pages. The number of logical pages stored in aphysical page thus reflects the number of bits stored per cell. In oneembodiment, the individual pages may be divided into segments and thesegments may contain the fewest number of cells that are written at onetime as a basic programming operation. One or more logical pages of dataare typically stored in one row of memory cells. A page can store one ormore sectors. A sector includes user data and overhead data.

An alternative arrangement to a conventional two-dimensional (2-D) NANDarray is a three-dimensional (3-D) array. In contrast to 2-D NANDarrays, which are formed along a planar surface of a semiconductorwafer, 3-D arrays extend up from the wafer surface and generally includestacks, or columns, of memory cells extending upwards. Various 3-Darrangements are possible. In one arrangement a NAND string is formedvertically with one end (e.g. source) at the wafer surface and the otherend (e.g. drain) on top. In another arrangement a NAND string is formedin a U-shape so that both ends of the NAND string are accessible on top,thus facilitating connections between such strings. Examples of suchNAND strings and their formation are described in U.S. PatentPublication Number 2012/0220088 and in U.S. Patent Publication Number2013/0107628, which are hereby incorporated by reference in theirentirety. In general, operation of 3-D NAND arrays is similar tooperation of 2-D NAND arrays and 3-D NAND arrays may be operated as SLCor MLC memories.

All-Bit, Full-Sequence MLC Programming

FIG. 6A-6C illustrate an example of programming a population of 4-statememory cells. FIG. 6A illustrates the population of memory cellsprogrammable into four distinct distributions of threshold voltagesrespectively representing memory states “E”, “A”, “B” and “C”. FIG. 6Aillustrates the initial distribution of “erased” threshold voltages foran erased memory. FIG. 613 illustrates an example of the memory aftermany of the memory cells have been programmed. Essentially, a cellinitially has an “erased” threshold voltage and programming will move itto a higher value into one of the three zones demarcated by verifylevels vV₁, vV₂ and vV₃. In this way, each memory cell can be programmedto one of the three programmed states “A”, “B” and “C” or remainun-programmed in the “erased” state. As the memory gets moreprogramming, the initial distribution of the “erased” state as shown inFIG. 6C will become narrower and the erased state is represented by the“0” state.

A 2-bit code having a lower bit and an upper bit can be used torepresent each of the four memory states. For example, the “E”, “A”, “B”and “C” states are respectively represented by “11”, “01”, “00” and‘10”. The 2-bit data may be read from the memory by sensing in“full-sequence” mode where the two bits are sensed together by sensingrelative to the read demarcation threshold values rV₁, rV₂ and rV₃ inthree sub-passes respectively.

Memory Systems

In many memory systems, multiple memory dies, or memory chips, areconnected to a memory controller through a shared memory bus so thatthey can be efficiently managed as part of large-scale memory system.For example, four, eight, or sixteen memory dies may be connected tosuch a bus. A memory controller may have more than one such bus, e.g. amemory controller may manage eight or sixteen busses, each with eight orsixteen dies. The numbers of dies and busses in such arrangements may bevery large, for example in Solid State Drives (SSDs) which are oftenused for mass storage applications. Aspects of the present invention maybe applied to such arrangements regardless of the number of busses orthe number of dies per bus. Memory dies in such systems may be planarNAND, 3-D memory (including charge-storage memories and resistivememories), or other types of memory.

A memory controller may access memory dies on a shared bus to provide ahigh degree of parallelism, for example by striping data across dies sothat while one or more die is busy writing data from an on-chip bufferto nonvolatile memory cells, subsequent data is being sent to anotherdie. Individual memory dies may perform various on-chip operationswithout occupying the memory bus so that the memory bus may beefficiently shared. However, efficient management of multiple dies canbecome quite complex as data is spread across multiple dies on one ormore busses.

FIG. 7 shows an arrangement in which a flash memory bus 701 is shared byfour flash memory dies 703 a-d (examples provided here largely refer toflash memory, but it will be understood that aspects of the disclosuremay apply to various forms of nonvolatile memory). Four die queues 705a-d are maintained, corresponding to the four flash dies. Each queuecontains contexts for a corresponding die, where a context is aninstruction for a particular die to perform a task (e.g. execution of ahost command such as a host write command may generate multiple contextsper die for multiple dies). A flash management layer 707 manages accessto the dies by selecting contexts from corresponding die queues so thatdata is moved efficiently between the flash dies and a host interface709.

In some memory controllers, data that is being transferred between ahost interface and a memory bus may be subject to some operations whilein the memory controller. For example it is common to use ErrorCorrection Code (ECC) to encode data that is received from a host priorto storage in a memory array. The data may later be decoded when it isread out from the memory array and errors may be detected and corrected.Examples of codes used include Reed-Solomon code, Hamming code, BCH, andLow Density Parity Check (LDPC). It is also common to apply Exclusive OR(XOR) operations to portions of data prior to storage so that if onesuch portion of data becomes corrupted (e.g. uncorrectable by ECC) thenit may be recovered by XORing other portions of data and stored XORoutput. In some memory systems, data may be randomized or scrambledprior to storage (and descrambled after reading from the memory array).Data may also be encrypted prior to storage and alter decrypted when itis read. Various other logical operations may be used in particularmemory systems. Data may travel along a datapath between a hostinterface and a memory bus (in either direction) through multipledatapath units, each datapath unit performing a different operation onthe data.

In a simple arrangement, sufficient dedicated datapath units areprovided for each memory bus to process all data between the memory busand the host interface. Such a static arrangement is relatively simpleto design and manage. However, it may be more efficient to sharedatapath units between busses (e.g. by using one ECC engine for two ormore busses) in a more dynamic arrangement. Each datapath unit may haveits own queue, or queues, of contexts so that each acts somewhatindependently according to their respective queues. Each queue maycontain contexts relating to different operations in different dies(which may be on the same bus or on different busses). Datapath unitsmay process such contexts according to some algorithm (e.g. round-robinfrom die to die). Some datapath units may be used for some data but notfor other data (e.g. XORing may only be required if ECC fails). Somedatapath units may have a fixed throughput (e.g. a given number of bytesper second) while others may have a variable throughput (e.g. throughputof an ECC machine may depend on the bit error rate of the data).Managing such resources in an efficient manner is challenging.

FIG. 8 shows an example of an arrangement in which datapath units A, B,and C are located between a memory bus 811 and a host interface 813 (ahost interface may also be considered as a datapath unit as it is alongthe datapath between the memory bus and a host bus). A data cache 815 isconnected to host interface 813. Each datapath unit has its respectivequeue (Queues A, B, and C, which may each include separate queues fordifferent dies) and between datapath units are buffers (Buffers A, B,and C) for holding data that has been operated on by a precedingdatapath unit and is awaiting a subsequent datapath unit. It will beunderstood that data travels in both directions along the datapathbetween the host and the memory dies (i.e. from host interface 813 tomemory bus 811, and from memory bus 811 to host interface 813).

According to an aspect of the present invention, when a datapath unitselects a context from its queue for execution, it does not always do soblindly, without regard to operations of other datapath units. Instead,there is some communication between datapath units that allowscoordination of datapath units so that they are more efficiently uses.For example, a datapath unit may send an output to one or more otherdatapath units indicating that it is currently operating on some datathat is part of a data stream. A datapath unit receiving such an output,and that is downstream from the sender of the output, may thenprioritize contexts associated with the data stream. Thus, a series ofdatapath units along a datapath may prioritize a data stream in responseto an output from the first datapath unit along the datapath.

In another embodiment, a datapath control unit helps to prioritizecontexts for multiple datapath units in a coordinated manner. Thus,instead of having each datapath unit independently operating on its ownqueue of contexts, datapath units may receive prioritization informationfrom a datapath control unit and then determine an order of execution ofcontexts in its queue in light of the prioritization information. Thismaintains flexibility while providing coordination between datapathunits.

Direct Communication

FIG. 9A shows an example of a memory controller 921 that includes threedatapath units that are operated in a coordinated manner, a flashinterface (flash DMA) 923, ECC machine (e.g. applying LDPC) 925, and anencryption/decryption machine 927. A host requests a portion of dataconsisting of a series of Flash Management Units (FMUs), where a FMU isthe smallest readable unit of data and corresponds to an ECC word (i.e.FMUs can be individually read and decoded). FMUs 0-6 are requested in ahost request (Tag X) 929. When the first datapath unit along thedatapath, in this case flash DMA 923, operates on the first data unit(FMU 0), it broadcasts an output 931 that indicates that it is startingto process data in response to host request 929. Downstream datapathunits 925, 927 may then prioritize contexts associated with host request923 so that they rapidly process the corresponding data units (FMU 0-6)from buffers. This may mean deferring other contexts that are notrelated to host request 929.

The broadcast 931 does not require downstream datapath units to stop allother operations and become dedicated to the data for the host request929 in this example. In some cases, a datapath unit may have thecapacity to handle multiple threads without slowing down a particularthread. For example, where an ECC machine is shared among a large numberof busses it may have sufficient capacity to perform ECC decoding formultiple busses at the same time by interleaving or otherwise sharingresources (i.e. it can process data at a speed equal to the datatransfer rate of multiple busses). The broadcast output may be treatedas a command that forces datapath units to act on data of for the hostrequest, or alternatively may be treated as an indicator of prioritythat is not binding (i.e. that the datapath unit can ignore undercertain conditions and is not forced to obey).

One problem with using a broadcast command relates to the tail of astream of data. When the datapath unit that is the source of the outputhas finished operating on data associated with the host request itceases sending the corresponding output. However, the tail of the data(i.e. the last data unit or units) may still be undergoing operations inother datapath units that are downstream of the source of the output.These datapath units may then cease prioritizing the data of the hostrequest so that the pipeline formed by coordinated datapath units breaksup and there may be significant delay in processing the tail andreturning the processed data to the host.

FIG. 9B shows the example of FIG. 9A at a point where the flashinterface has finished FMU 6 and has transferred it to a buffer. Becausethere is no output broadcast to the ECC machine 925 orencryption/decryption unit 927, these datapath units may start othercontexts that are not related to the data of the host command. FMU 6 isstill awaiting processing by the ECC machine 925 and FMU 5 is awaitingprocessing by the encryption/decryption unit 927 (FMUs 0-3 are in cacheawaiting transfer to the host). Delay in processing FMUs 5 and 6 mayhave significant impact on the overall time to complete the host request929. Thus, this solution may not be ideal for all situations.

Datapath Control Unit

In an alternative arrangement, a datapath control unit provides somecoordination between datapath units by providing information regardingprioritization which can be used by the datapath units in determiningwhich context to execute. A datapath control unit, like datapath units,may be formed as a dedicated circuit or may be formed by firmware thatconfigures a more general purpose circuit for its specific function.

FIG. 10 shows an example of a datapath control unit 541 that is incommunication with three datapath units of a memory controller 543, aflash interface 545, ECC machine 547, and an encryption/decryption unit549. Datapath control unit 541 is also in communication with a datacache 551 (and may be in communication with a host interface unit 553and/or other components).

One application of a datapath control unit is to allow streaming of datawithout a tail effect as described with respect to a broadcast approachabove. For example, in FIG. 10 the flash interface 545 may send anoutput to the datapath control unit 541 when it begins operating on thefirst unit of a host request. The datapath control unit 541 may thenprovide prioritization information to the other datapath units (547,549) to indicate that a stream of data is coming through and should beprioritized. In this case, when the tail of the data stream passesthrough the flash interface, the data of the stream may continue to beprioritized so that the complete stream is returned to the host rapidly.

A datapath control unit may use any suitable technique for communicatingprioritization information to datapath units. FIG. 11 shows an examplein which datapath control unit 541 maintains a table 561 that containspriority information. Each line in the table includes a tag (e.g.Command tag X, Y, Z) that corresponds to a host command (e.g. read orwrite command) or controller operation. Each line also includesprioritization information in the form of weighting (e.g. weight=A, orB) and categorization information (e.g. cat=0 or 1). Each tag has acorresponding weight (which may be just a few bits) that indicates thepriority of the corresponding command or operation indicated by the tag.Each tag is also assigned a category as either a host command or acontroller operation. This allows separate treatment of host andcontroller operations in this example. It will be understood thatdifferent systems of prioritization may be used (e.g. separatehost/controller categories may not be needed, more than two categoriescould be used to distinguish different types of commands, and weightingmay have any number of levels, A, B, C, D, . . . etc.). Otherinformation may also be stored in such a table in some cases.

A prioritization table may be maintained using any suitable hardware. Inthe present example, a Content Addressable Memory (CAM) is used, thougha cache or RAM table, or other arrangement may also be suitable in somecases. Entries may be arranged in any suitable format including a linkedlist, linear organization tag, by weight, by category, or by some otherinformation.

When a datapath unit (e.g. datapath unit 549) needs to determine whichcontext to begin next, it may check its queue, or queues, 563 and see ifthere are contexts that are in condition for execution (e.g. dataalready in buffers etc.). If there are no contexts in condition forexecution then the datapath unit may become idle. If there is only onecontext in condition for execution then the datapath unit may startexecuting it. If there are two or more contexts that are in conditionfor execution then the datapath unit may refer to the prioritizationtable 561 to determine which context to execute first. Each contextcorresponds to a host command or controller operation that has acorresponding tag entry in the prioritization table 561 so that theprioritization can easily be looked up. A CAM facilitates rapid lookupof such information.

Prioritization Schemes

A datapath control unit may apply a prioritization scheme in order toefficiently move data along a datapath that includes multiple datapathunits, each with a separate context queue. In the above example of ahost read command, a high prioritization would be given to contextsassociated with data that is read in response to the host read commandso that the data travels rapidly from datapath unit to datapath unit(while other contexts may be put aside by being given relatively lowpriorities).

FIGS. 12A-12C show an example of a prioritization scheme that is used toreorder data between a memory bus and a host interface. Three queues671, 673, 675, are shown for three successive datapath units along adatapath. The first queue 671 (queue for a flash interface) shows that acontext corresponding to request N is executed and the correspondingdata is toggled out to the next datapath unit (through buffers). Datacorresponding to the next context, N+1, is in the flash read cache andis available to the flash interface. A context associated with RequestN+3 is moved to a high priority in queue 671 at this point (e.g. bychanging its weight as indicated by a prioritization table in datapathcontrol unit CAM). Because data corresponding to request N+1 is alreadyin flash read cache, this data is processed by the flash interface.However, Requests N+2 and N+3 have not started yet. The datapath unitmay then determine that because of its higher priority, the dataassociated with Request N+3 should be operated on before data associatedwith Request N+2.

FIG. 12B shows how a context associated with data N+3 is operated on outof order in the first datapath unit. The datapath unit informs thedatapath controller that it has changed the order and is proceeding withRequest N+3.

FIG. 12C shows how a datapath control unit changes prioritization forqueues of additional datapath units after the first datapath unitindicates that it is proceeding with N+3 and after prior data (e.g. N,N+1, etc.) is already processed by the additional datapath units. Thus,the prioritization change propagates along the datapath with data N+3(rather than changing all along the datapath at once, which could causedisruption if other datapath units were still operating on earlierdata). In this way, a datapath control unit can coordinate a change inprioritization in a safe manner. While the example of FIGS. 12A-C showsprioritization of contexts associated with a request N+3, it will beunderstood that this approach may be applied to any amount of data andmay be used for a variety of reprioritization operations.

In one example, data that is received from a memory bus out-of-order maybe reordered by a datapath control unit so that it reaches a data cachefor the host interface in order and may be rapidly sent to the host.Some memory systems allow data to be read from memory dies out-of-order(e.g. skipping dies that are busy and reading opportunistically fromavailable dies). This data may then be stored in data cache and sent toa host in order. However, this may require significant data cache andmay reduce read performance. Reordering such data as it proceeds along adatapath between the memory bus and the data cache may reduce data cacheusage and may improve read performance. In some memory systems, such assome SSDs, host bandwidth, or host bus bandwidth, may be lower than thecumulative memory system bandwidth so that saturating the host bus isimportant for good performance.

FIG. 13 shows data in a memory system (e.g. SSD) passing through variousdatapath units along a datapath that serves two data busses 381, 383,each serving four memory dies. At each stage, the data is reorderedbased on priorities (weightings) associated with particular commands.Four read commands of different length are sent by the host R, B, G, andV. Corresponding data portions r, b, g, and v are read from the memorydies. The data portions are distributed across dies in a manner thatrequires serial access to particular dies to execute an individual readcommand. For example, execution of command R (32 KB) requires four readoperations (8 KB each) but these reads are concentrated in two diesconnected to memory bus 381 as indicated by circled data “r” entries inqueues for the respective dies. In order to take advantage ofparallelism, other data (for subsequent commands B and V) is read fromother dies in parallel as indicated by corresponding entries in otherqueues. Data portions g are only read after data portions r becausereading them requires access to the same dies. When data passes throughan ECC machine (eLDPC) the order of the data is modified according tothe prioritization order R>G>B>V. The data is modified again accordingto the same prioritization when passing through an encryption/decryption(AES) unit, and again when passing through a host interface unit (HDMA).Thus, data portions r rise in order as the data passes through datapathunits and data portions g similarly rise, while data portions b and vdrop down in order. While data may not be ordered in the exact order ofhost commands at the end of a series of such reordering steps, thechange in order may be sufficient to provide performance improvement.

While examples above refer to increasing priority of certain operations,in some cases it may be efficient to reduce priority of certainoperations. For example, where a particular command is going to bedelayed for some reason, contexts associated with the delayed commandmay be reduced in priority because executing them rapidly will notreduce the time for execution of the command. For example, if access toa particular die is required in order to complete execution of acommand, and the die is likely to be busy for an extended period oftime, then there may be little benefit, or no benefit, in completingcontexts associated with the command rapidly. Instead, they may becompleted as low-priority contexts as resources allow.

In some cases, data is first stored in binary form (one bit per cell)and then “folded” into MLC format (two or more bits per cell). Thisallows data to be stored rapidly initially and then later, when time isless critical, to be copied into a more space-efficient format. Examplesof folding are described in U.S. Pat. Nos. 8,144,512 and 8,468,294,which are hereby incorporated by reference in their entirety. Folding ofdata may take an extended period of time so that when folding is carriedout in a particular die then the die becomes unavailable for an extendedperiod so that commands that require access to the die may be lowered inpriority.

In some cases, there is a danger that low priority commands orcontroller operations may remain unexecuted because available resourcesare continuously in use for high priority commands. This may beundesirable. For example, certain housekeeping operations (e.g. garbagecollection) may not be urgent but if not performed may result in poorperformance. According to an example, commands increase in priority asthey remain uncompleted over time. A timer may be used to determine howlong a command has remained uncompleted, or the number of other commandscompleted may be counted, or some other mechanism may be used toincrement weights to ensure that commands rise in priority the longerthey remain uncompleted.

CONCLUSION

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form disclosed. Many modificationsand variations are possible in light of the above teaching. Thedescribed embodiments were chosen in order to best explain theprinciples of the invention and its practical application, to therebyenable others skilled in the art to best utilize the invention invarious embodiments and with various modifications as are suited to theparticular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

It is claimed:
 1. A method of operating a nonvolatile memory controllercomprising: maintaining a first queue of contexts for a first datapathunit that acts on data between a host interface of the memory controllerand a nonvolatile memory bus; maintaining a second queue of contexts fora second datapath unit that acts on data in series with the firstdatapath unit between the host interface and the nonvolatile memory bus;generating an output that indicates a current operation of the firstdatapath unit, the output sent from the first datapath unit during thecurrent operation; and in response to the output, changing priority ofcontexts of the second queue of contexts for the second datapath unit.2. The method of claim 1 wherein the output is broadcast directly fromthe first datapath unit to the second datapath unit and to at least athird datapath unit that acts on data in series with the first andsecond datapath units.
 3. The method of claim 1 wherein the output issent from the first datapath unit to a datapath control unit that is incommunication with the first datapath unit and the second datapath unit,the datapath control unit managing context prioritization for the firstdatapath unit and the second datapath unit.
 4. The method of claim 3wherein the datapath control unit manages context prioritization bymaintaining a weighted table of commands, priorities of contextsassociated with commands changing according to weighting of theirrespective commands.
 5. The method of claim 3 wherein the outputindicates that the first datapath unit is acting on data in response toa host read command and wherein weighting associated with the host readcommand is modified to prioritize contexts associated with the host readcommand in the second queue of contexts for the second datapath unit. 6.The method of claim 5 wherein modification of the weighting associatedwith the host read command also prioritizes contexts associated with thehost read command in at least a third queue of contexts for a thirddatapath unit in series with the first and second datapath units.
 7. Themethod of claim 6 wherein the first datapath unit is a flash interfacemodule that is connected to the nonvolatile memory bus, the seconddatapath unit is an Error Correction Code (ECC) machine, and the thirddatapath unit is one of: an Exclusive OR (XOR) unit, or a dataencryption/decryption unit.
 8. The method of claim 3 wherein the outputindicates that the first datapath unit is acting on data in response toa host write command and wherein weighting associated with the hostwrite command is modified to prioritize contexts associated with thehost write command in the second queue of contexts for the seconddatapath unit.
 9. The method of claim 8 wherein the first datapath unitis a host interface unit and the second datapath unit is one of: an ECCmachine, an XOR unit, or a data encryption/decryption unit.
 10. Themethod of claim 3 wherein the output indicates that a command should beweighted so that contexts associated with the command have lower orhigher priority.
 11. The method of claim 3 further comprising: thedatapath control unit applying a weighting scheme to provide data insequential order to the host interface of the memory controller when thedata is received out of sequential order from the nonvolatile memorybus.
 12. The method of claim 3 further comprising: the datapath controlunit applying a weighting scheme to stream data from the host interfaceto the memory bus, or to stream data from the memory bus to the hostinterface.
 13. The method of claim 11 further comprising: the datapathcontrol unit applying a time-based adjustment of weighting so thatcommands increase in priority according to the amount of time theyremain uncompleted.
 14. A nonvolatile memory controller comprising: ahost interface; a memory bus; a first datapath unit between the hostinterface and the memory bus; a first context queue that containscontexts for the first datapath unit; a second datapath unit connectedin series with the first datapath unit between the host interface andthe memory bus; a second context queue that contains contexts for thesecond datapath unit; and a datapath control unit directly connected tothe first datapath unit and directly connected to the second datapathunit, the datapath control unit prioritizing contexts in the first andsecond context queues for the first and second datapath units byproviding prioritization information to the first and second datapathcontrol units in parallel.
 15. The nonvolatile memory controller ofclaim 14 wherein the datapath control unit comprises a tag cache thatcontains entries corresponding to commands, each entry having aweighting that indicates priority of corresponding contexts in the firstand second context queues.
 16. The nonvolatile memory controller ofclaim 15 wherein the tag cache is formed by a Content Addressable Memory(CAM).
 17. The nonvolatile memory controller of claim 14 wherein thefirst datapath unit is a nonvolatile memory interface unit and thesecond datapath unit is an Error Correction Code (ECC) unit.
 18. Thenonvolatile memory controller of claim 17 further comprising at least athird datapath unit connected in series with the first and seconddatapath units between the host interface and the memory bus.
 19. Thenonvolatile memory controller of claim 18 wherein the at least a thirddatapath unit includes at least one of; (a) an Exclusive OR (XOR) unit,or (b) an encryption unit.
 20. The nonvolatile memory controller ofclaim 14 further comprising a first set of data buffers connected to thefirst datapath unit and a second set of data buffers connected to thesecond set of datapath unit.
 21. The nonvolatile memory controller ofclaim 14 wherein the memory bus is a NAND flash memory bus.
 22. Thenonvolatile memory controller of claim 14 wherein the memory bus is athree-dimensional nonvolatile memory bus.
 23. A nonvolatile memorysystem comprising: a three dimensional nonvolatile memory array; amemory bus connected to the three dimensional nonvolatile memory; and amemory controller connected to the memory bus, the memory controllercomprising: a host interface; a first datapath unit between the hostinterface and the memory bus; a first context queue that containscontexts for the first datapath unit; a second datapath unit connectedin series with the first datapath unit between the host interface andthe memory bus; a second context queue that contains contexts for thesecond datapath unit; and a datapath control unit that is directlyconnected to the first datapath unit and directly connected to thesecond datapath unit, the datapath control unit prioritizing contexts inthe first and second context queues for the first and second datapathunits in parallel.
 24. The nonvolatile memory system of claim 23 whereinthe three dimensional nonvolatile memory array is a three dimensionalNAND memory array that includes NAND strings that extend in a directionperpendicular to a primary surface of a substrate.
 25. The nonvolatilememory system of claim 23 wherein the three dimensional nonvolatilememory array is a Resistive Random Access Memory (ReRAM) memory arraythat includes resistivity switching storage elements.